An AC-Coupled 1st-order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition.

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this paper, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range and electrode DC offset cancellation. An AC-coupled 1st-order digitally-intensive Δ-ΔΣ architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits and a digital control, has been fabricated in 22-nm FDSOI CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 µW, and an input-referred noise of 7.7 ± 0.4 µVrms in the AP band and 11.9 ± 1.1 µVrms in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

A Micropower Chopper CBIA Using DSL-Embedded Input Stage With 0.4 V EO Tolerance for Dry-Electrode Biopotential Recording.

A chopper instrumentation amplifier (IA) dedicated for bio-potential acquisition usually requires a linearized input stage for large electrode offset voltage accommodation. This linearization leads to excessive power consumption when sufficiently low input-referred noise (IRN) is required. We present a current-balance IA (CBIA) without the need for the input stage linearization. It uses two transistors to operate as an input transconductance stage and a dc-servo loop (DSL) at the same time. An off-chip capacitor completes the DSL by ac coupling the source terminals of the input transistors via chopping switches realizing a sub-Hz high-pass cutoff frequency for dc rejection. Fabricated in a 0.35-µm CMOS process, the proposed CBIA occupies 0.41 mm2 and consumes 1.19 µW from a 3 V dc supply. Measurements show that the IA achieves an input-referred noise of 0.91 µVrms over 100 Hz bandwidth. This corresponds to a noise efficiency factor of 2.22. Typical CMRR of 102.1 dB is achieved for zero offset and degraded to 85.9 dB when a ±0.3 V input offset was applied. Gain variation of 0.5% is maintained within the range of ±0.4 V input offset. The resulting performance meets well with the requirement for ECG and EEG recording using dry electrodes. A demonstration for the use of the proposed IA on a human subject is also provided.

A Compact Sub-µW CMOS ECG Amplifier With 57.5-MΩ Zin, 2.02 NEF, 8.16 PEF and 83.24-dB CMRR.

This paper presents a compact DDA-based fully-differential CMOS instrumentation amplifier dedicated for micro-power ECG monitoring. Only eight transistors are employed to realize a power-efficient current-sharing DDA. A RC network (using MOS pseudo resistors and poly capacitors) forms feedback loops around the DDA creating an ac-only amplification. The proposed amplifier is dc-coupled via gate terminals of the p-channel input transistors. It thus achieves sufficiently high input impedance over the entire ECG frequency range. Fabricated in a 0.35-µm CMOS process, the proposed amplifier occupies 0.0712 mm2. It operates from a 2 V dc supply with 336 nA current consumption. Measurements show that the amplifier attains its input impedance of 57.5 MΩ at 150 Hz and achieves 1.54 µVrms input-referred noise over 0.1-300 Hz. Noise and power efficiency factors are 2.02 and 8.16, respectively. At 50 Hz, the mean CMRR of 83.24 dB is obtained from 11-chip measurement. Experiments performed on a human subject confirm the functionality of the proposed amplifier in a real measurement scenario.

Comparison of speech processing strategies for the design of an ultra low-power analog bionic ear.

Miniaturizing area and power consumptions of cochlear prosthetic devices is strongly required for full implantation. In this paper, several speech encoding strategies are studied and compared in order to find a compact speech processor that allows for full implantation and is able to convey both time and frequency components of the incoming speech to a set of electrical pulse stimuli. The study covers the widely recognized continuous time interleaved sampling (CIS) and strategies that convey the temporal fine structure (TFS), including race-to-spike asynchronous interleaved sampling (AIS), phase-locking (PL) using zero-crossing detection (ZCD), and PL using a peak-picking (PP) technique. To estimate the performances of the four systems, a spike-based reconstruction algorithm is employed to retrieve the original sounds after being processed by different strategies. The correlation factors between the reconstructed and original signals imply that strategies that convey TFS outperform CIS. Among them, the peak picking technique combines good performance with great compactness since envelope detectors are not required.